1. Field of the Invention
The present invention relates to programmable memory arrays, and particularly semiconductor integrated circuit memory arrays incorporating passive element memory cells, and even more particularly a three-dimensional memory array incorporating such memory cells.
2. Description of the Related Art
Certain passive element memory cells exhibit re-writable characteristics. For example, in certain memory cells programming may be achieved by forward biasing the memory cell (e.g., with reference to the polarity of a diode therewithin) with a voltage of approximately 6-8V, while erase may be achieved by reverse biasing the memory cell with a voltage of approximately 10-14V. These high voltages require use of special high voltage CMOS transistors within the word line and bit line decoders. These high-voltage transistors do not scale well as the memory cell word line and bit line pitch decreases. This is particularly problematic for 3D memory technology, in which the sheer density of word lines and bit lines exiting the array, and which must be interfaced with a word line and bit line driver, makes even more important the ability to provide decoder circuits, and particularly the word line and bit line driver circuits, compatible with ever smaller array line pitches, yet capable of impressing a sufficiently high voltage across a selected memory cell.